library ieee;

use ieee.std_logic_1164.all;
use std.textio.all;
use work.all;

entity VDU_tb is
end VDU_tb;

architecture behavior of VDU_tb is
  component VDU
    port (	CLK, RESET, START, STOP	:	in Bit;
			DELAY, DATA_IN			:	in bit_vector(3 downto 0);
			DATA_OUT				:	out bit_vector(3 downto 0));
  end component;
  for all: VDU use entity work.VDU;
  
  signal clk_t, reset_t, start_t, stop_t  : Bit;
  signal delay_t, datain_t, dataout_t     : bit_vector(3 downto 0);
  
begin
  dutVDU: VDU port map(CLK => clk_t, RESET => reset_t, START => start_t, STOP => stop_t, DELAY => delay_t, DATA_IN => datain_t, DATA_OUT => dataout_t);
    
  process
		variable vline: line;
		variable v1: bit;
		variable v2: bit;
		variable v3: bit;
		variable v4: bit_vector(3 downto 0);
		variable v5: bit_vector(3 downto 0);
		file invect: text is "input4.txt";
	begin
	  clk_t <= '0';
	  while not (endfile(invect)) loop
	    readline(invect, vline);
	    read(vline, v1);
	    read(vline, v2);
	    read(vline, v3);
	    read(vline, v4);
	    read(vline, v5);
	    reset_t <= v1;
	    start_t <= v2;
	    stop_t <= v3;
	    delay_t <= v4;
	    datain_t <= v5;
	    
	    wait for 50 ns;
	    clk_t <= '1';
	    wait for 50 ns;
	    clk_t <= '0';
	  end loop;
	end process;  
end behavior;